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I/O Ports with Key Wake-up
Key Wake-Up Input Filter
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor I/O Ports with Key Wake-up 135
this time interval is shorter than t
KWSP
, the majority voting logic may treat
the two consecutive pulses as a single valid pulse.
The filter is shared by all the KWU pins. Hence any valid triggering level
on any KWU pin is seen by the filter. The timing specification applies to
the input of the filter.
Figure 10-1. STOP Key Wake-up Filter (falling edge trigger) timing
Glitch, filtered out, no STOP wake-up
Valid STOP Wake-Up pulse
t
KWSTP
min.
t
KWSP
Minimum time interval between pulses to be recognized as single pulses
t
KWSTP
max.
- MC68Hc912D60A 1
- MC68HC912D60C 1
- MC68HC912D60P 1
- MC68HC912D60A 3
- 4 Freescale Semiconductor 4
- List of Paragraphs 5
- Table of Contents 10
- Section 11. Clock Functions 10
- Section 12. Oscillator 10
- Section 17. MSCAN Controller 12
- List of Figures 15
- List of Tables 19
- 1.1 Contents 23
- 1.2 Introduction 23
- General Description 24
- are devices similar to 24
- 1.4 Features 24
- Features 25
- 1.5 Ordering Information 27
- 1.6 Block Diagrams 29
- 2.1 Contents 31
- 2.2 Introduction 31
- 2.3 Programming Model 31
- Central Processing Unit 32
- 2.4 Data Types 33
- 2.5 Addressing Modes 33
- 2.6 Indexed Addressing Modes 35
- 2.7 Opcodes and Operands 36
- 3.1 Contents 37
- 3.4 Power Supply Pins 42
- 3.5 Signal Descriptions 44
- Signal Descriptions 45
- 3.6 Port Signals 52
- Port Signals 53
- Section 4. Registers 61
- Registers 62
- 5.1 Contents 71
- 5.2 Introduction 71
- 5.3 Operating Modes 71
- Operating Modes 73
- 5.4 Background Debug Mode 74
- MODE — Mode Register $000B 75
- Internal Resource Mapping 77
- RESET:00000001 80
- 5.6 Memory Maps 83
- . MC68HC912D60A Memory Map 83
- 6.1 Contents 85
- 6.2 Introduction 85
- Bus Control and Input/Output 86
- 6.4 Registers 86
- Section 7. Flash Memory 97
- 7.3 Overview 98
- 7.5 Flash EEPROM Arrays 98
- 7.6 Flash EEPROM Registers 99
- Flash Memory 100
- 7.7 Operation 100
- Programming the Flash EEPROM 101
- 7.9 Erasing the Flash EEPROM 103
- 7.10 Stop or Wait Mode 103
- Section 8. EEPROM Memory 105
- EEPROM Memory 106
- EEPROM Programmer’s Model 107
- EXTALi (hz) x 35 109
- EEPROM Control Registers 111
- Bit 7654321Bit 0 113
- RESET: 10000000 113
- 8.6 Program/Erase Operation 115
- 8.7 Shadow Word Mapping 115
- 9.1 Contents 119
- 9.2 Introduction 119
- Resets and Interrupts 120
- 9.3 Maskable interrupts 120
- 9.4 Latching of Interrupts 121
- 9.6 Resets 124
- 9.7 Effects of Reset 126
- 9.8 Register Stacking 127
- 9.9 Customer Information 128
- 10.1 Contents 129
- 10.2 Introduction 129
- I/O Ports with Key Wake-up 130
- Clock Functions 138
- 11.3 Clock Sources 138
- 11.4 Phase-Locked Loop (PLL) 139
- PLLFLG — PLL Flags $003B 157
- 11.8 Clock Divider Chains 162
- 11.10 Real-Time Interrupt 167
- 11.11 Clock Monitor 167
- RTIF0000000 169
- RESET: 00000000 169
- Oscillator 176
- EXTAL-XTAL 189
- Oscillator Design Guidelines 193
- EXTAL-VSS 205
- Guidelines 206
- 13.1 Contents 207
- 13.2 Introduction 207
- Pulse Width Modulator 208
- Introduction 209
- PWM Register Description 211
- PWCNTx — PWM Channel Counters 217
- 13.4 PWM Boundary Cases 222
- 14.1 Contents 223
- 14.2 Introduction 223
- Enhanced Capture Timer 224
- 14.4 Timer Registers 233
- BIT 7654321BIT 0 245
- 000000PAOVFPAIF 245
- RESET: 0 0 0 0 0 0 0 0 249
- Timer Registers 253
- 15.1 Contents 263
- 15.2 Introduction 263
- Multiple Serial Interface 264
- 15.3 Block diagram 264
- 15.6 Port S 285
- 16.1 Contents 289
- 16.2 Introduction 289
- Freescale Interconnect Bus 290
- 16.3 Push-pull sequence 290
- 16.4 Biphase coding 291
- 16.5 Message validation 292
- STOP START 293
- 16.6 Interfacing to MI Bus 294
- Interfacing to MI Bus 295
- 16.7 MI Bus clock rate 296
- 16.8 SCI0/MI Bus registers 296
- SCI0/MI Bus registers 297
- MSCAN Controller 304
- 17.3 External Pins 304
- 17.4 Message Storage 305
- Message Storage 307
- Identifier Acceptance Filter 311
- 17.6 Interrupts 314
- 17.8 Low Power Modes 316
- 1. X means don’t care 317
- Low Power Modes 319
- 17.9 Timer Link 320
- 17.10 Clock System 321
- 17.11 Memory Map 324
- RESET 00000000 333
- RESET 0 0 000000 335
- 18.1 Contents 349
- 18.2 Introduction 349
- Analog-to-Digital Converter 350
- HC12 ATD BLOCK 350
- Modes of Operation 351
- 18.4 Functional Description 352
- Functional Description 353
- 18.5 ATD Operational Modes 354
- 18.9 ATD Registers 358
- ATD Registers 363
- 19.1 Contents 377
- 19.2 Introduction 377
- 19.3 Instruction Queue 377
- Development Support 378
- 19.4 Background Debug Mode 379
- Background Debug Mode 381
- 19.5 Breakpoints 395
- Breakpoints 397
- 19.6 Instruction Tagging 402
- 20.1 Contents 405
- 20.2 Introduction 405
- Electrical Specifications 406
- 20.3 Tables of Data 406
- Table 20-4. Supply Current 409
- Table 20-12. Control Timing 413
- Tables of Data 415
- Table 20-15. SPI Timing 422
- Table 20-18. Key Wake-up 426
- 22.1 Contents 437
- Mask Set Changes 443
- 23.4 Clock Circuitry 444
- 23.5 Pseudo Stop Mode 444
- 23.6 Oscillator 444
- 23.7 PLL 445
- Glossary 447
- Revision History 457
- How to Reach Us: 460
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